1. Field of the Invention
The present invention relates to the fabrication of integrated circuit structures and, in particular, to the fabrication of an ultra-small, sub-lithographic bipolar transistor emitter using conventional lithography techniques.
2. Discussion of the Related Art
A bipolar transistor is a three-terminal device that can, when properly biased, controllably vary the magnitude of the current that flows between two of the transistor's terminals. The three terminals include a base terminal, a collector terminal and an emitter terminal. The charge carriers, which form the current, flow between the collector terminal and the emitter terminal; variations in the voltage applied to the base terminal cause the magnitude of the current to vary.
Due to the increasing demand for battery-powered devices, there is a need for a bipolar transistor that utilizes less power. Lower power consumption can be obtained in a bipolar transistor by reducing the maximum current that can flow between the collector and emitter terminals. One approach for reducing the maximum current is to reduce the size of the base-to-emitter junction, preferably to sub-lithographic feature sizes.
The literature reports a method that allows the formation of polysilicon ridge emitter transistors down to 0.1 micron width without relying on advanced lithography tools. See “Poly Emitter Transistor (PRET): Simple Low Power Option to a Bipolar Process”, by Wim van der Wel, et al., IEDM 93-453, 1993, pp. 17.6.1-17.6.4. However, this method utilizes two polysilicon layers, as shown in the FIG. 1A-1C fabrication sequence.
As shown in FIG. 1A, the van der Wel et al. technique begins in the conventional manner with an integrated circuit structure that includes a trench isolation structure 100 formed in a semiconductor substrate to define a substrate active device region 102. An n-type collector region 104 is formed in the substrate active device region 102 and a p-type base region 106 is formed above the collector region 104. A layer of silicon dioxide 108 is formed to extend over the active device region 102. A first layer of n-doped polysilicon is then formed over the layer of dielectric material 108. The polysilicon layer and the underlying silicon dioxide 108 are then patterned to define a poly1 emitter region 110 that extends over the p-type base region 106 but is separated from the base region 106 by intervening dielectric material 108. A second layer of n-doped polysilicon is then formed over the above-described structure, as further shown in FIG. 1A.
As shown in FIG. 1B, the poly2 layer is then anisotropically etched to define poly2 sidewalls 112 on the poly1 emitter region 110. An subsequent annealing step results in diffusion of n-type dopant from the poly2 sidewall formed on the base region 106 into the p-type base region 106 to define an n-type emitter junction 114 in the base region 106. Dielectric sidewalls 116 are then formed to electrically isolate the poly2 sidewalls. Finally, salicide films 118 are formed on the base region 106 and on the poly1 emitter region 110, as shown in FIG. 1C.
Although the van der Wel technique described above results in small emitters, it has the following disadvantages. First, the slope of the poly1 emitter region is critical to success of this method; the slope could affect the width of the emitter (i.e. the poly2 sidewalls) significantly, introduce large variability in the emitter width across the wafer and, therefore, result in performance variability. Second, the possible large variability of the poly emitter ridge, i.e. the poly2, could in turn introduce large variability in the oxide spacers, which could cause shorts between the emitter and the base regions during the salicidation step. Third, emitter n-type dopant diffusion is less in the structure, compared to conventional single poly device architectures, due to the possible presence of a poly1/poly2 interfacial barrier in the emitter structure, as shown in FIG. 1C.
Thus, there is a need for a low-power bipolar transistor with a sub-lithographic base-to-emitter junction that reduces, or preferably eliminates, the previously-described drawbacks.